Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

IEEE Symposium on Low Power Electronics

Volumn , Issue , 1996, Pages 353-358

  Hiraki, Mitsuru ^a   Bajwa, Raminder S ^a   Kojima, Hirotsugu ^a   Gorny, Douglas J ^a   Nitta, Ken ichi ^a   Shridhar, Avadhani ^a   Sasaki, Katsuro ^a   Seki, Koichi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; DECODING; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER SUPPLIES TO APPARATUS; RANDOM ACCESS STORAGE; REDUCED INSTRUCTION SET COMPUTING; SUBROUTINES;

DECODED INSTRUCTION BUFFER; MULTIMEDIA PROCESSORS; POWER CONSUMPTION;

PIPELINE PROCESSING SYSTEMS;

EID: 0030402187     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)