Low Voltage Operation of Sub-Quarter Micron W-Polycide Dual Gate CMOS with Non-Uniformly Doped Channel

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 583-586

  Sayama, H ^a   Kuroi, T ^a   Shimizu, S ^a   Shirahata, M ^a   Okumura, Y ^a   Inuishi, M ^a   Miyoshi, H ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; CMOS INTEGRATED CIRCUITS; OXIDE FILMS; THRESHOLD VOLTAGE; ELECTRIC CURRENTS; ELECTRODES; ETCHING; GATES (TRANSISTOR); INTERDIFFUSION (SOLIDS); ION IMPLANTATION; OXIDATION; OXIDES; RANDOM ACCESS STORAGE; SEMICONDUCTOR DOPING; SEMICONDUCTOR STORAGE; SPUTTERING;

BARRIER OXIDES; DOPANT-DIFFUSION; DUAL-GATE CMOS; GATE DEPLETION; GATE ELECTRODES; INTER DIFFUSION; LOW VOLTAGE OPERATION; POLYCIDE; THERMAL BUDGET; UNIFORMLY-DOPED CHANNELS;

REFRACTORY METAL COMPOUNDS; CMOS INTEGRATED CIRCUITS;

CURRENT DRIVABILITY; NONUNIFORMLY DOPED CHANNEL; POLYSILICON; THRESHOLD VOLTAGE;

EID: 0030398598     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554051     Document Type: Conference Paper

References (6)

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