Design methodology of deep submicron cmos devices for 1v operation

IEICE Transactions on Electronics

Volumn E79-C, Issue 12, 1996, Pages 1720-1724

  Oyamatsu, Hisato ^a   Kinugawa, Masaaki ^a   Kakumu, Masakazu ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

CMOS; Low power dissipation; Low voltage; Threshold voltage

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; MOSFET DEVICES;

SWITCHING TRANSIENT CURRENT; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0030398511     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (14)

1. M. Kakumu and M. Kinugawa, Power-supply voltage impact on circuit performance for half and lower submi-crometer CMOS LSI, IEEE Trans. Electron Devices, vol. 37, no. 8, p. 1902, 1990.
2. W. H. Chane, B. Davari, M. R. Wordeman, Y. Taur, C. C. -H. Hsu, and M. D. Rodriguez, A high performance 0.25 pm CMOS technology (0(11), IEEE Trans. Electron Devices, vol. 39, pp. 959-967, 1992.
3. G. A. Sai-Halasz, M. R. Wordman, D. P. Kern, E. Ganin, S. A. Rishton, H. Y. Ng, D. Zicherman, D. Moy, T. H. P. Chang, and R. H. Dennard, Experimental technology and characterization of self aligned 0.1 pm-gate length low temperature operation NMOS devices, IEEE Int. Electron Device Meeting Tech. Dig., p. 397, 1987.
4. Y. Mii, S. Wind, Y. Taur, Y. Lii, D. Klaus, and J. Bucchignano, An ultra-low power 0.1 ftm CMOS, Symp. VLSI Technology Dig. Tech. Papers, p. 9, 1994.
5. R. Yan, D. Monroe, J. Weis, A. Mujtaba, and E. Westerwick, Reducing operating voltage from 3, 2, to 1 volt and below-challenges and guidelines for possible solutions, IEEE Int. Electron Devices Meeting Tech. Dig., p. 55, 1995.
6. Z. Chen, J. Burr, J. Shott, and J. D. Plummer, Optimization of quarter micron MOSFETs for low voltage/low power applications, IEEE Int. Electron Devices Meeting Tech. Dig., p. 63, 1995.
7. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideant, E. Bassous, and A. R. LeBlanc, Design of ion-implanted MOSFET's with very small physical dimensions, IEEE J. Solid State Circuits, vol. SC-9, pp. 256-268, 1974.
8. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, p. 506, 1985.
9. A. G. Sabnis and J. T. Clements, Characterization of the electron mobility in the inverted 100 Si surface IEEE Int. Electron Devices Meeting Tech. Dig., p. 18, 1979.
10. S. C. Sun and J. D. Plummer, Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces, IEEE Trans. Electron Devices, vol. ED27, no. 10, p. 8, 1980. IEEE Int. Electron Devices Meeting Tech. Dig., p. 18, 1979.
11. C. G. Sodini, P. K. Ko, and J. L. Moll, The effect of high fields on MOS devices and circuit performance, IEEE Trans. Electron Devices, vol. ED31, no. 10, p. 1386, 1984. [12] S. Takagi, M. Iwase, and A. Toriumi, On the universality of inversion-layer mobility in N- and P-channel MOSFET's, IEEE Int. Electron Devices Meeting Tech. Dig., p. 398, 1988.
12. T. Mizuno, M. Iwase, H. Niiyama, T. Shibata, K. Fujisaki, T. Nakasugi, A. Toriumi, and Y. Ushiku, Performance fluctuations of O.lpm MOSFETs-limitation of 0.1 m ULSis, Symp. VLSI Technology Dig. Tech. Papers, p. 13, 1994.
13. H. Oyamatsu, M. Kinugawa, and M. Kakumu, Design methodology of deep submicron CMOS devices for 1 V operation, Symp. VLSI Technology Die. Tech. Papers, p. 89, 1993.
14. K. K. Ng and W. T. Lynch, Analysis of gate-voltage dependent series resistance of MOSFETs, IEEE Trans. Electron Device, vol. ED34, p. 503, 1987. [16] T. Kobayashi and T. Sakurai, Self-adjusting threshold voltage scheme (SATS) for low voltage high speed operation, Proc. IEEE 1994 CICC, p.271~ 1994.