Zero X-Y low temperature cofired ceramic substrate using Ag and AgPd conductors for flip-chip bonding

Proceedings of the IEEE/CPMT International Electronic Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 1996, Pages 156-161

  Itagaki, Minehiro ^a   Bessho, Yoshihiro ^a   Eda, Kazuo ^a   Ishida, Toru ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CERAMIC MATERIALS; ELECTRIC CONDUCTORS; ELECTRONICS PACKAGING; FIRING (OF MATERIALS); GOLD; LOW TEMPERATURE EFFECTS; MULTICHIP MODULES; PALLADIUM ALLOYS; SHRINKAGE; SINTERING; SOLDERING; SUBSTRATES;

BONDABILITY; CHIP SIZE PACKAGES (CSP); LOW TEMPERATURE COFIRED CERAMIC (LTCC) SUBSTRATE; STUD BUMP BONDING (SBB);

FLIP CHIP DEVICES;

EID: 0030398256     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)