Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding

IEEE International SOI Conference

Volumn , Issue , 1996, Pages 36-37

  Tong, Q Y ^a   Lee, T H ^a   Kim, W J ^a   Tan, T Y ^a   Goesele, U ^a   You, H M ^a   Yun, W ^a   Sin, Johnny K O ^a  

^a MAX PLANCK INSTITUTE OF MICROSTRUCTURE PHYSICS   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; BONDING; CHEMICAL VAPOR DEPOSITION; INTERFACIAL ENERGY; OXIDES; PLASMA APPLICATIONS; POLISHING; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; SUBSTRATES; SURFACE MEASUREMENT;

CHEMICAL MECHANICAL POLISHING (CMP); DIRECT BONDING;

VLSI CIRCUITS;

EID: 0030394560     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)