CostAS - KGD process cost modeling

Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon

Volumn , Issue , 1996, Pages 313-322

  Ammann, Daniel ^a   Thiel, Andreas ^a   Habiger, Claus ^a   Troster, Gerhard ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

AVAILABILITY; COSTS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION;

KNOWN GOOD DIES (KGD);

MULTICHIP MODULES;

EID: 0030389245     PISSN: 10632204     EISSN: None     Source Type: None    
DOI: 10.1109/ICISS.1996.552438     Document Type: Conference Paper

References (11)

1. C. M. Habiger R. M. Lea Hybrid-WSI: A Massively Parallel Computing Technology? IEEE Computer 50 61 April 1993
2. C. M. Habiger An Investigation into the Cost-Effectiveness of Multi-Chip Modules for Massively Parallel Computing Applications 1995 Hartung-Gorre Verlag Konstanz
3. C. Dislis L. P. Jalowiecki Test strategies for multi-chip modules based on economics considerations 1995 WSI
4. P. A. Sandborn A. R. Parikh Tradeoff Analysis and Partitioning in multiple Board/MCM Systems 1995 ICEMCM
5. C. Peacock H. Bolouri C. Habiger Multichip Module Yield Enhancement using Passive Substrate Fault Tolerance ISIS 1996
6. S. J. Hedge C. J. Hall An experimental Fault-Tolerant Active Substrate MPC MCM Using Standard Gate Array Technology 1995 WSI
7. C. M. Habiger R. M. Lea Reducing Cost and Ensuring On-time Delivery of HybridWSI Massively Parallel Computing Modules 1994 WSI
8. Micron: SRAM Die Datasheet S25A September 1995 Micron Techonology Inc.
9. SmartDie Product Overview Intel Corporation http://www.intel.com/design/smartdie/