Circular self-test path for FSMs

IEEE Design and Test of Computers

Volumn 13, Issue 4, 1996, Pages 50-60

  Corno, Fulvio ^a,b   Prinetto, Paolo ^a,b   Reorda, Matteo Sonza ^a,b  

^a POLITECNICO DI TORINO   (Italy)

^b IEEE

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; FINITE AUTOMATA; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MATHEMATICAL MODELS; RANDOM ACCESS STORAGE;

BINARY DECISION DIAGRAMS (BDD); BUILT IN SELF TEST (BIST); CIRCULAR SELF TEST PATH (CSTP); FINITE STATE MACHINES (FSM);

INTEGRATED CIRCUIT TESTING;

EID: 0030388604     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.544536     Document Type: Review

References (12)

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