A Highly Stable SRAM Memory Cell with Top-Gated P-N Drain Poly-Si TFTs for 1.5V Operation

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 283-286

  Hayashi, Fumihiko ^a   Ohkubo, Hiroaki ^a   Takahashi, Toshifumi ^a   Horiba, Shinichi ^a   Noda, Kenji ^a   Uchida, Tetsuya ^a   Shimizu, Toshiyuki ^a   Sugawara, Norikazu ^a   Kumashiro, Shigetaka ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CYTOLOGY; MEMORY ARCHITECTURE; POLYCRYSTALLINE MATERIALS; SEMICONDUCTOR STORAGE; BIPOLAR TRANSISTORS; ELECTRIC CURRENTS; GATES (TRANSISTOR); RANDOM ACCESS STORAGE; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; THIN FILM TRANSISTORS;

BIPOLAR ACTION; CELL-BE; CELL/B.E; CELL/BE; HIGH SPEED; HIGHLY STABLES; LOW VOLTAGES; PERFORMANCE; POLY-SI TFTS; SRAM MEMORY CELLS;

STATIC RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE;

LIGHTLY DOPED OFFSET; MEMORY CELL; TOP GATED STRUCTURES;

EID: 0030387666     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553585     Document Type: Conference Paper

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