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Volumn , Issue 40, 1996, Pages

Petri nets and asynchronous circuit design

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; BOOLEAN FUNCTIONS; COMPUTER SIMULATION; COMPUTER SOFTWARE; CONSTRAINT THEORY; ENCODING (SYMBOLS); GRAPHICAL USER INTERFACES; LOGIC CIRCUITS; LOGIC GATES; OPTIMIZATION; PETRI NETS;

EID: 0030386635     PISSN: 09633308     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (2)

References (18)
  • 5
    • 0012022507 scopus 로고
    • Assassin: A synthesis system for asynchronous control circuits
    • IMEC, Sept. User and Tutorial manual
    • C. Ykman-Couvreur, B. Lin and H. De Man, Assassin: A synthesis system for asynchronous control circuits. Technical Report, IMEC, Sept. 1994, User and Tutorial manual.
    • (1994) Technical Report
    • Ykman-Couvreur, C.1    Lin, B.2    De Man, H.3
  • 6
    • 0024645936 scopus 로고
    • Petri Nets: Properties, analysis and application
    • T. Murata, Petri Nets: Properties, analysis and application. Proc. of IEEE, 77(4), pp. 541-574 (1989).
    • (1989) Proc. of IEEE , vol.77 , Issue.4 , pp. 541-574
    • Murata, T.1
  • 9
    • 84994842734 scopus 로고
    • Petri net analysis using Boolean manipulation
    • June 1994, Zaragoza, Spain, LNCS 815, Springer-Verlag, Berlin
    • E. Pastor, O. Roig, J. Cortadella and R.M. Badia. Petri net analysis using Boolean manipulation. Proc. Int. Conf. Appl. and Theory of Petri Nets, June 1994, Zaragoza, Spain, LNCS 815, Springer-Verlag, Berlin, 1994, pp. 416-435.
    • (1994) Proc. Int. Conf. Appl. and Theory of Petri Nets , pp. 416-435
    • Pastor, E.1    Roig, O.2    Cortadella, J.3    Badia, R.M.4
  • 10
    • 0001176166 scopus 로고
    • Stubborn attack on state explosion
    • A. Valmari. Stubborn attack on state explosion. Form. Meth. in Syst. Des., Vol.1, 1991, pp. 297-322.
    • (1991) Form. Meth. in Syst. Des. , vol.1 , pp. 297-322
    • Valmari, A.1
  • 12
    • 0029482463 scopus 로고
    • Combining partial orders and symbolic traversal for efficient verification of asynchronous circuits
    • Chiba, Japan, August-September
    • A. Semenov and A. Yakovlev. Combining partial orders and symbolic traversal for efficient verification of asynchronous circuits. Proc. IFIP Int. Conference on Computer Hardware Description Languages, (CHDL'95), Chiba, Japan, August-September 1995, pp. 567-573.
    • (1995) Proc. IFIP Int. Conference on Computer Hardware Description Languages, (CHDL'95) , pp. 567-573
    • Semenov, A.1    Yakovlev, A.2
  • 17
    • 5544279885 scopus 로고
    • PROD: - A Pr/T-net reachability analysis tool
    • Series B. Helsinki University of Technology, June
    • P. Grönberg, M. Tiusanen and K. Varpaaniemi. PROD: - A Pr/T-net reachability analysis tool. Series B. Tech. Rep., No. 11, Helsinki University of Technology, June 1993.
    • (1993) Tech. Rep. , vol.11
    • Grönberg, P.1    Tiusanen, M.2    Varpaaniemi, K.3
  • 18
    • 0003901784 scopus 로고
    • Technical report, Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Illinois. USA
    • Ultrasan, user's manual, version 3.0. Technical report, Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Illinois. USA, 1995.
    • (1995) Ultrasan, User's Manual, Version 3.0


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.