Sub-0.25 μm ultra-thin SOI CMOS with a single N+ gate process for low-voltage and low-power applications

IEEE International SOI Conference

Volumn , Issue , 1996, Pages 80-81

  Raynaud, C ^a   Faynot, O ^a   Pelloie, J L ^a   Tedesco, S ^a   Ullmann, B ^a   Dunne, B ^a   Guegan, G ^a   Lerme, M ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); OSCILLATORS (ELECTRONIC); RANDOM ACCESS STORAGE; SILICON ON INSULATOR TECHNOLOGY; ULTRATHIN FILMS;

RING OSCILLATORS;

CMOS INTEGRATED CIRCUITS;

EID: 0030386362     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)