Interface controlled IDP process technology for 0.3 μm high-speed bipolar and BiCMOS LSIs

Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting

Volumn , Issue , 1996, Pages 181-184

  Hashimoto, Takashi ^a   Kumauchi, Takahiro ^a   Jinbo, Tomoko ^a   Watanabe, Kunihiko ^a   Yoshida, Eiichi ^a   Miura, Hideo ^a   Shiba, Takeo ^a   Tamaki, Yoichi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS SILICON; BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; CRYSTALLIZATION; CURRENT VOLTAGE CHARACTERISTICS; GAIN CONTROL; INTERFACES (MATERIALS); LSI CIRCUITS; PHOSPHORUS; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; STRESSES;

BIPOLAR/COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (BICMOS); EMITTER LAYER;

BIPOLAR TRANSISTORS;

EID: 0030385448     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)