The HIPERLAN equalizer ASIC complexity and its relationship with the training header

Wireless Personal Communications

Volumn 3, Issue 4, 1996, Pages 421-427

  Daneshrad, Babak ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; ELECTRIC FILTERS; EQUALIZERS; LEAST SQUARES APPROXIMATIONS; LOCAL AREA NETWORKS; PACKET SWITCHING; SIGNAL FILTERING AND PREDICTION;

HIGH PERFORMANCE RADIO LOCAL AREA NETWORKS; PACKET PROCESSING DELAY; RECURSIVE LEAST SQUARED ALGORITHMS; TAP COEFFICIENT; TRAINING HEADERS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0030385213     PISSN: 09296212     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF00461150     Document Type: Article

References (11)

1. T. Cox and F. Natali, "Further Results on the Application of Equalization, Forward Error Correction Coding, and Antenna Diversity in the Hiperlan Environment," Ulm, Germany, Doc. No. RES10/TTG/94/Ulm-26, April 1994.
2. A. Nix, M. Li, M. Beach, I. Johnson, T. Wilkinson and S. Barton, "A Summary of the Laura Air-Interface Technique," Ulm, Germany, Doc. No. RES 10/TTG/94/Ulm-30, April 1994.
3. E. Khayata et al., Minutes of Hiperlan Meeting, Paris, France, Sept. 1994.
4. R. Joshi, B. Daneshrad and H. Samueli, "A VLSI Architecture for a Single-Chip 5-Mbaud QAM Receiver," Proceedings of IEEE Globecom 92, Orlando, FL, pp. 1265-1268, 1992.
5. R. Joshi and H. Samueli, "A 100 MHz, 5 Mbaud QAM Decision-Feedback Equalizer for Digital Television Applications," to appear in the International Solid State Circuits Conference, 1995.
6. F. Lu and H. Samueli, "A 60-Mbaud, 480-MBit/s, 256 QAM decision-feedback equalizer in 1.2 mm CMOS," Proc. IEEECICC, pp. 29.1.1-29.1.4, 1992.
7. H. Samueli, B. Daneshrad, R. Joshi, B. Wong, and H. T. Nicholas, III, "A 64-Tap CMOS Echo Canceller/Decision Feedback Equalizer for 2B1Q High Bit-Rate Digital Subscriber Line Transceivers," IEEE Journal on Selected Areas in Communications, vol. 9, pp. 839-847, 1991.
8. John G. Proakis, Digital Communications, McGraw Hill, 1989.
9. C. S. H. Wong, J. C. Rudell, G. T. Uehara and P. R. Gray, "A 50 MHz Eight-Tap Adaptive Equalizer for Partial-Response Channels," IEEE Journal of Solid-State Circuits, vol. 30, No. 3, pp. 228-234, 1995
10. A. Vandemeulebroecke, E. Vanzieleghem, T. Denayer and P. G. A. Jespers, "A New Carry-Free Division Algorithm and its Application to a Single-Chip 1024-b RSA Processor," IEEE Journal of Solid-State Circuits, vol. 25, No. 3, pp. 748-756, 1990.
11. Marcho Annaratone, Digital CMOS Circuit Design, Kluwer Academic Publishers, 1986.