Modification of parasitic edge leakage in LOCOS-isolated SOI MOSFETS using back-gate stress

IEEE International SOI Conference

Volumn , Issue , 1996, Pages 84-85

  Sherony, Melanie J ^a   Yang, Isabel Y ^a   Antoniadis, Dimitri A ^a   Doyle, Brian S ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; GATES (TRANSISTOR); LEAKAGE CURRENTS; OXIDATION; SILICON ON INSULATOR TECHNOLOGY; STRESSES;

BACKGATE STRESS; LOCAL OXIDATION OF SILICON (LOCOS); NMOS DEVICES; PARASITIC EDGE LEAKAGE; SOFTWARE PACKAGE MEDICI; SOFTWARE PACKAGE TSUPREM4;

MOSFET DEVICES;

EID: 0030385112     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)