A High-Density 6.9 sq. pm Embedded SRAM Cell in a High-Performance 0.25 μm-Generation CMOS Logic Technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 275-278

  Subbanna, S ^a   Agnello, P ^a   Crabbk, E ^a   Schulz, R ^a   Wu, S ^a   Tallman, K ^a   Saccamango, M J ^a   Greco, S ^a   McGahay, V ^a   Allen, A J ^a   Chen, B ^a   Cotler, T ^a   Eld, E ^a   Lasky, J ^a   Ng, H ^a   Ray, A ^a   Snare, J ^a   Su, L ^a   Sunderland, D ^a   Sun, J ^a   Davari, B ^a   more..

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT DESIGN; LITHOGRAPHY; LOGIC GATES; OPTIMIZATION; RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE;

0.25 ΜM; CMOS LOGIC; DESIGN RULES; HIGH-PERFORMANCE CMOS TECHNOLOGY; LOGIC TECHNOLOGY; PERFORMANCE; PHYSICAL DESIGN; POWER SUPPLY; SALICIDES; SRAM CELL;

CYTOLOGY; INTEGRATED CIRCUIT MANUFACTURE;

DAMASCENE LOCAL INTERCONNECT; SALICIDE TECHNOLOGY; SHALLOW TRENCH ISOLATION; ULTRAVIOLET LITHOGRAPHY;

EID: 0030382710     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553583     Document Type: Conference Paper

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