Prediction of circuit performance variations for deep submicron CMOS processes

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1996, Pages 140-148

  Gneiting, Thomas ^a   Jalowiecki, Ian ^a  

^a ESSLINGEN UNIVERSITY OF APPLIED SCIENCES   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; MOS DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE; STATISTICAL METHODS; SYNCHRONIZATION; ULSI CIRCUITS; VARIATIONAL TECHNIQUES;

SOFTWARE PACKAGE SPICE;

CMOS INTEGRATED CIRCUITS;

EID: 0030378517     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)