Unified VLSI architecture for decomposition and synthesis of discrete wavelet transform

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 1996, Pages 113-116

  Sheu, Ming Hwa ^a   Shieh, Ming Der ^a   Cheng, Shun Fa ^a  

^a NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; INTEGRATED CIRCUIT LAYOUT; WAVELET TRANSFORMS;

DISTRIBUTED ARITHMETIC METHOD; ELEMENTARY COMPUTING MODULE; THROUGHPUT RATE;

VLSI CIRCUITS;

EID: 0030370850     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)