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Volumn , Issue , 1996, Pages 1-15
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Does building-in reliability imply more or less wafer-level reliability testing?
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Author keywords
[No Author keywords available]
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Indexed keywords
INFORMATION USE;
INTEGRATED CIRCUIT MANUFACTURE;
RELIABILITY;
ULSI CIRCUITS;
BUILDING IN RELIABILITY (BIR) STRATEGY;
WAFER LEVEL RELIABILITY (WLR);
INTEGRATED CIRCUIT TESTING;
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EID: 0030362397
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (7)
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References (2)
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