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Volumn 3, Issue , 1996, Pages 1367-1370
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Low power pipelined FFT architecture for synthetic aperture radar signal processing
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER ARCHITECTURE;
COMPUTER SIMULATION;
FAST FOURIER TRANSFORMS;
PIPELINE PROCESSING SYSTEMS;
RANDOM ACCESS STORAGE;
SIGNAL PROCESSING;
DELAY LOCKED LOOP (DLL);
STATIC RANDOM ACCESS MEMORY (SRAM);
SYNTHETIC APERTURE RADAR;
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EID: 0030362074
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (2)
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References (8)
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