Parallel architecture for arithmetic coding and its VLSI implementation

Midwest Symposium on Circuits and Systems

Volumn 3, Issue , 1996, Pages 1309-1312

  Lee, Horng Yeong ^a   Lan, Leu Shing ^a   Sheu, Ming Hwa ^a   Wu, Chien Hsing ^a  

^a NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DIGITAL ARITHMETIC; ENCODING (SYMBOLS); PARALLEL ALGORITHMS; VLSI CIRCUITS;

ARITHMETIC CODING; VERY HIGH SPEED INTEGRATED CIRCUIT HARDWARE DESCRIPTION LANGUAGES;

PARALLEL PROCESSING SYSTEMS;

EID: 0030349671     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)