Overlay improvement through overlay modeling

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 2726, Issue , 1996, Pages 311-322

  Borodovsky, Yan ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Microlithography; Modeling; Overlay; Registration

Indexed keywords

ALIGNMENT; COMPUTER SIMULATION; ERROR CORRECTION; PROCESS CONTROL;

OVERLAY MODELING;

LITHOGRAPHY;

EID: 0030316215     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.240973     Document Type: Conference Paper

References (7)

1. Automated electrical measurements of registration errors on step and repeat optical lithography systems
2. Analysis of overlay distortion patterns
3. Matching performance for multiple wafer steppers using an advanced metrology procedure
4. Overlay control in submicron environment
5. Registration simulations and sampling strategies for large field lithorgraphy
6. Overlay process control for 16-Mb DRAM manufacturing
7. Improvement and application in 64M DRAM stepper