Gate etch induced diode leakage prevention with 7-nm CVD stacked gate dielectric

IEEE Electron Device Letters

Volumn 17, Issue 11, 1996, Pages 528-530

  Perera, Asanga H ^a,b   Tseng, Hsing Huang ^a,b  

^a IEEE

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CHEMICAL VAPOR DEPOSITION; ELECTRIC RESISTANCE; ETCHING; GATES (TRANSISTOR); LEAKAGE CURRENTS; MOS DEVICES; MOSFET DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR DIODES; SEMICONDUCTOR GROWTH; TRANSMISSION ELECTRON MICROSCOPY;

GATE ETCH INDUCED DIODE LEAKAGE PREVENTION; MICROPORE MISALIGNMENT; STACKED GATE DIELECTRIC; STRESS COMPENSATION; THERMALLY GROWN OXIDE;

DIELECTRIC DEVICES;

EID: 0030290312     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.541770     Document Type: Article

References (7)

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