Safety-critical systems built with COTS

Computer

Volumn 29, Issue 11, 1996, Pages 54-60

  Profeta III, Joseph A ^a,d,e,f,q   Andrianos, Nikos P ^a,e,g,h   Yu, Bing ^a,e,g,i,j   Johnson, Barry W ^b,f   DeLong, Todd A ^b,k   Guaspari, David ^c,l,m,n   Jamsek, Damir ^c,o,p  

^a Union Switch and Signal ^*

^b UNIVERSITY OF VIRGINIA   (United States)

^c Odyssey Research Associates

^d Advanced Technology Group (ATG)

^e UNIVERSITY OF PITTSBURGH   (United States)

^f IEEE

^g Advanced Technology Group   (United States)

^h NATIONAL TECHNICAL UNIVERSITY OF ATHENS   (Greece)

ⁱ ZHEJIANG UNIVERSITY   (China)

^j SHANGHAI JIAO TONG UNIVERSITY   (China)

^k MARIETTA COLLEGE   (United States)

^l TEXAS TECH UNIVERSITY   (United States)

^m RENSSELAER POLYTECHNIC INSTITUTE   (United States)

ⁿ UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^o Syracuse University

^p SYRACUSE UNIVERSITY   (United States)

^q Union Switch & Signal Company   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ACCIDENT PREVENTION; ALGORITHMS; COMPUTER CONTROL SYSTEMS; COMPUTER HARDWARE; COMPUTER SOFTWARE; ERRORS; MICROCOMPUTERS; TECHNOLOGY;

CATASTROPHIC SYSTEM FAILURE; COMMERCIAL OFF THE SHELF; CORRECTNESS CRITERIA; MICROPROCESSOR BASED CONTROL SYSTEMS; SAFETY CRITICAL SYSTEMS; VITAL FRAMEWORK;

COMPUTER SYSTEMS;

EID: 0030289246     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.544238     Document Type: Review

References (7)

1. P. Forin, "Vital Coded Microprocessor Principles and Application for Various Transit Systems," IFAC-GCCT, Paris, France, Sept. 1989, pp. 79-84.
2. D. Rutherford, "A Vital Digital Control System with a Calculable Probability of an Unsafe Failure," IEEE Press, Piscataway, N.J. 1990, pp. 1-11.
3. B.W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems, Addison-Wesley, Reading, Mass., 1989.
4. C. Anfinson and F.T. Luk, "A Linear Algebraic Model of Algorithm-Based Fault Tolerance," IEEE Trans. Computers, Dec. 1988, pp. 1599-1604.
5. P. Banerjee and J.A. Abraham, "Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems," IEEE Trans. Computers, Apr. 1986, pp. 296-306.
6. D. Gu, D.J. Rosenkrantz, and S.S. Ravi, "Construction of Check Sets for Algorithm-Based Fault Tolerance"IEEE Trans. Computers, June 1994, pp. 641-650.
7. N. Halbwachs et al., "The Synchronous Data Flow Programming Language LUSTRE," Proc. IEEE, Sept. 1991, pp. 1305-1320.