CMOS NAND and NOR Schmitt circuits

Microelectronics Journal

Volumn 27, Issue 8, 1996, Pages 757-765

  Dokić, Branko L ^a  

^a UNIVERSITY OF BANJA LUKA   (Bosnia and Herzegovina)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; HYSTERESIS; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; NAND CIRCUITS; SEQUENTIAL CIRCUITS; SPURIOUS SIGNAL NOISE; TRANSISTORS;

NOISE IMMUNITY; NOR CIRCUITS; REGENERATIVE CIRCUITS; SCHMITT CIRCUITS; SUPPLY VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0030288942     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/0026-2692(96)00009-2     Document Type: Article

References (6)

1. B.L. Dokić, CMOS Schmitt triggers, IEE Proc., 131(5) (Oct. 1984) 197-202.
2. B.L. Dokić and Z.V. Bundalo, Regenerative logic circuits with CMOS transistors, Int. J. Electron., 58(6) (1985) 907-920.
3. Zhenhua Wang, CMOS adjustable Schmitt triggers, IEEE Trans. Instrum., 40(3) (June 1991) 601-605.
4. Daejeong Kim, Joongsik and Wonchan Kim, A new waveform reshaping circuit; an alternative approach to Schmitt trigger, IEEE J. Solid-State Circuits, 28(2) (Feb. 1993) 162-164.
5. J. Exalto, HCMOS Schmitt-trigger applications, Electron. Components Applications, 7(3) (1985) 144-151.
6. B.L. Dokić, Influence of series and parallel transistors on DC characteristics of CMOS logic circuits, Microelectronics J., 13(2) (March/April 1982) 25-30.