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Volumn 11, Issue 3, 1996, Pages 303-307

Low-voltage CMOS subthreshold four-quadrant tripler

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; DIFFERENTIAL AMPLIFIERS; ELECTRIC CURRENTS; FREQUENCY MULTIPLYING CIRCUITS; MATHEMATICAL MODELS; MOSFET DEVICES; SIGNAL PROCESSING;

EID: 0030285489     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF00240491     Document Type: Article
Times cited : (2)

References (11)
  • 1
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    • S. C. Qin and R. L. Geiger, "A + 5-V CMOS analog multiplier." IEEE J. Solid-State Circuits. SC-22, pp. 1143-1146, Dec. 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , pp. 1143-1146
    • Qin, S.C.1    Geiger, R.L.2
  • 2
    • 0025448598 scopus 로고
    • An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers
    • June
    • H. J. Song and C. K. Kim, "An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers." IEEE J. Solid-State Circuits. SC-25, pp. 841-847, June 1990.
    • (1990) IEEE J. Solid-State Circuits , vol.SC-25 , pp. 841-847
    • Song, H.J.1    Kim, C.K.2
  • 3
    • 0028448789 scopus 로고
    • CMOS four quadrant multiplier using bias feedback techniques
    • June
    • S. I. Lhi and Y. S. Hwang, "CMOS four quadrant multiplier using bias feedback techniques." IEEE Journal of Solid-State Circuits. SC-29, pp. 750-752, June 1994.
    • (1994) IEEE Journal of Solid-State Circuits , vol.SC-29 , pp. 750-752
    • Lhi, S.I.1    Hwang, Y.S.2
  • 4
    • 0024479756 scopus 로고
    • Introduction to implantable biomedical IC design
    • L. J. Stotts, "Introduction to implantable biomedical IC design." IEEE Circuits and Devices Mag. pp. 12-18, 1989.
    • (1989) IEEE Circuits and Devices Mag , pp. 12-18
    • Stotts, L.J.1
  • 5
    • 0026186337 scopus 로고
    • Realization of 1-V active filter using a linearization technique employing plurality of emitter-coupled pairs
    • July
    • H. Tanimoto, M. Koyama, and Y. Yoshida, "Realization of 1-V active filter using a linearization technique employing plurality of emitter-coupled pairs." IEEE J. Solid-State Circuits. SC-26, pp. 937-944, July 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.SC-26 , pp. 937-944
    • Tanimoto, H.1    Koyama, M.2    Yoshida, Y.3
  • 6
    • 0028338159 scopus 로고
    • A bipolar four-quadrant analog qnarter-square multiplier consisting of unbalanced emitter-coupled pairs and expansions of its input ranges
    • Jan.
    • K. Kimura, "A bipolar four-quadrant analog qnarter-square multiplier consisting of unbalanced emitter-coupled pairs and expansions of its input ranges." IEEE J. of Solid-State Circuits. SC-29, pp. 46-55, Jan. 1994.
    • (1994) IEEE J. of Solid-State Circuits , vol.SC-29 , pp. 46-55
    • Kimura, K.1
  • 7
    • 0019597235 scopus 로고
    • A three-level broad-banded monolithic analog multiplier
    • Aug.
    • J. Choma, JR., "A three-level broad-banded monolithic analog multiplier." IEEE J. Solid-State Circuits. SC-16, pp. 392-399, Aug. 1981.
    • (1981) IEEE J. Solid-State Circuits , vol.SC-16 , pp. 392-399
    • Choma Jr., J.1
  • 11
    • 0029252916 scopus 로고
    • CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs
    • Feb.
    • S. I. Liu and C. C. Chang, "CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs." Int. J. Electronics. 78, pp. 327-332, Feb. 1995.
    • (1995) Int. J. Electronics , vol.78 , pp. 327-332
    • Liu, S.I.1    Chang, C.C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.