A PRML read/write channel IC using analog signal processing for 200 Mb/s HDD

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 11, 1996, Pages 1817-1829

  Parsi, Kaveh ^a,b,d,e,f,g   Burns, Robert P ^b,h   Chaiken, Alan ^b,e,i   Chambers, Mark J ^{a,b,j,k,l,m,n,o}   Forni, William R ^a,b,k,n   Harnishfeger, David ^b,k,n   Kaylor, Scott ^{a,b,p,q,r,s,t}   Pennell, Micheal J ^b,j,k,u   Perez, Jose O ^b,v   Rao, Narendra ^b,c   Rohrbaugh, Mark ^b   Ross, Mike ^a,b   Stuhlmiller, Gary L ^a,b  

^a IEEE

^b MOTOROLA INC   (United States)

^c Datapath Systems Inc   (United States)

^d BOSTON UNIVERSITY   (United States)

^e Department of Obstetrics Gynecology   (United States)

^f Digit Equip Corp Adv Vax Devmt

^g Mass Storage Analog Design Group

^h IOWA STATE UNIVERSITY   (United States)

ⁱ MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^j ARIZONA STATE UNIVERSITY   (United States)

^k UNIVERSITY OF CALIFORNIA   (United States)

^l RAYTHEON COMPANY   (United States)

^m TEXAS INSTRUMENTS   (United States)

ⁿ Mass Storage Signal Processing Group

^o SAN JOSE STATE UNIVERSITY   (United States)

^p NORTHERN ARIZONA UNIVERSITY   (United States)

^q Medtronic's Micro Rel Division

^r Silicon Systems

^s VLSI Technology

^t Mass Storage Read Channel Group

^u Mass Storage Design Group

^v GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; DEMODULATORS; ELECTRIC FILTERS; EQUALIZERS; HARD DISK STORAGE; LEAST SQUARES APPROXIMATIONS;

ANALOG SIGNAL PROCESSING; CONTINUOUS TIME FILTER; HARD DISK DRIVE; READ WRITE INTEGRATED CIRCUIT;

CMOS INTEGRATED CIRCUITS;

EID: 0030285064     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/jssc.1996.542407     Document Type: Article

References (9)

1. R. Cideciyan et al., "A PRML system for digital magnetic recording," IEEE J. Select. Areas Commun., vol. 10 no. 1, pp. 38-56, Jan. 1992.
2. R. A. Richetta et al., "A 16 MB/s PRML read/write data channel," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 78-79.
3. R. Yamasaki et al., "A 72 Mb/s PRML disk drive channel chip with an analog sampled-data signal processor," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 278-279, 352.
4. K. Bull et al., "A CMOS analog continuous-time delay line with adaptive delay-time control," IEEE J. Solid-State Circuits, vol. SC-23, no. 3. pp. 759-766, June 1988.
5. J. O. Voorman et al., "Bipolar integration of analog gyrator and Laguerre type filters (transconductor-capacitor filters)," in Proc. EC-CTD'83, Stuttgart, Sept. 1983, pp. 108-110.
6. P. M. Clarkson Optimal and Adaptive Signal Processing. Boca Raton, FL: CRC Press, 1993.
7. S. Dasgupta, C. R. Johnson, Jr., and A. M. Baksho, "Sign-sign LMS convergence with independent stochastic inputs," IEEE Trans. Inform. Theory, vol. 36, pp. 197-201, 1990.
8. K. Sone et al., "A 10-b 100 Msample/s pipelined subranging BiCMOS ADC," IEEE J. Solid-State Circuits, vol. 28, no. 12, p. 1182, Dec. 1993.
9. Bell Syst. Tech. J., vol. 51. no. 2, Feb. 1972 - see Ferguson's PR-IV algorithm.