Built-in self-test: Assuring system integrity

Computer

Volumn 29, Issue 11, 1996, Pages 39-45

  Könemann, Bernd ^a,b,c   Bennetts, Ben ^a,d,e   Jarwala, Najmi ^a,b,f,g   Nadeau Dostie, Benoit ^a,f,h,i  

^a LogicVision ^*  (United Kingdom)

^b LogicVision Inc   (United States)

^c TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

^d Joint Test Action Group

^e UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^f IEEE

^g UNIVERSITY OF MASSACHUSETTS   (United States)

^h LogicVision Canada Inc   (Canada)

ⁱ UNIVERSITÉ DE SHERBROOKE   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTAL DEFECTS; ELECTRONIC EQUIPMENT; ELECTRONIC EQUIPMENT TESTING; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT MANUFACTURE; MATERIALS TESTING; MICROPROCESSOR CHIPS; SCANNING; SEMICONDUCTOR MATERIALS;

BUILT IN SELF TEST; EMBEDDED MEMORY; HARDWARE DEFECTS; LOGIC STRUCTURE; SCANNING TECHNOLOGY;

INTEGRATED CIRCUIT TESTING;

EID: 0030284874     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.544236     Document Type: Review

References (11)

1. H. Hao and R. Avra, "Structured Design for Debug - The SuperSPARC II Methodology and Implementation," Proc. Int'l Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1995, pp. 175-183.
2. H.W. Miller, " 'Design for Test' via Standardized Design and Display Techniques," Electronics Test, Oct. 1983, pp. 108-116.
3. K.P. Parker, The Boundary Scan Handbook, Kluwer Academic Publishers, Norwell, Mass., 1992.
4. P.H. Bardell, W. McAnney, and J. Savir, Built-In Test for VLSI: Pseudo-Random Techniques, John Wiley & Sons, Somerset, N.J., 1987.
5. E.B. Eichelberger et al., Structured Logic Testing, Prentice-Hall, Englewood Cliffs, N.J., 1991.
6. B.H. Seiss, P.M. Trouborst, and M.H. Schulz, "Test Point Insertion for Scan-Based BIST," Proc. European Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1991, pp. 253-262.
7. A.J. Van de Goor, Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Somerset, N.J., 1991.
8. S. Sunter, "The P1149.4 Mixed Signal Test Bus: Costs and Benefits," Proc. Int'l Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1995, pp. 444-450.
9. H. Hulvershorn, P. Soong, and S. Adham, "Linking Diagnostic Software to Hardware Self-Test in Telecom Systems," Proc. Int'l Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1995, pp. 986-993.
10. E.C. Behnke, "3B21D BIST/Bscan System Diagnostic Test Story," Proc. Int'l Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1994, pp. 120-126.
11. R.E. Tulloss, "Leave the Wires to Last - Functional Evaluation of the IEEE Standard 1149.5 Module Test and Maintenance Bus," Proc. Int'l Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1995, pp. 797-806.