Serial storage architecture

IBM Journal of Research and Development

Volumn 40, Issue 6, 1996, Pages 591-601

  Judd, I D ^a,b,c   Murfet, P J ^a,c,d   Palmer, M J ^e  

^a Xyratex Technology Limited   (United Kingdom)

^b CHURCHILL COLLEGE   (United Kingdom)

^c IBM   (United States)

^d LOUGHBOROUGH UNIVERSITY   (United Kingdom)

^e Loughborough University ^*

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ERROR DETECTION; HARD DISK STORAGE; INTERACTIVE DEVICES; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; PERFORMANCE; RELIABILITY; USER INTERFACES;

INPUT OUTPUT DEVICES; SERIAL LINK; SERIAL STORAGE ARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 0030284813     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.406.0591     Document Type: Article

References (6)

1. "7133 and 7131 Serial Storage Architecture (SSA) Disk Subsystems," IBM Publication G522-2416.
2. "Serial Storage Architecture - Physical, SSA-PH1," ANSI Standard X3T10.1/1145D. This specification is available from Global Engineering, telephone 1-800-854-7179.
3. "Serial Storage Architecture - Transport Layer, SSA-TL1," ANSI Standard X3T10.1/989D. This specification is also available from Global Engineering.
4. "Serial Storage Architecture, SSA-S2P (ANSI SCSI-2 Protocol)," ANSI Standard X3T10.1/1121D. This specification is also available from Global Engineering.
5. I. Cidon and Y. Ofek, "MetaRing: A Full-Duplex Ring with Fairness and Spatial Reuse," IEEE Trans. Commun. COM-41, No. 1, 110-120 (January 1993).
6. A. X. Widmer and P. A. Franaszek, "A DC-Balanced, Partitioned Block, 8B/10B Transmission Code," IBM J. Res. Develop. 27, No. 5, 440-450 (September 1983).