Reliability improvement of single-poly quasi self-aligned BiCMOS BJTs using base surface arsenic compensation

Microelectronics Reliability

Volumn 36, Issue 11-12 SPEC. ISS., 1996, Pages 1827-1830

  Vendrame, L ^a,b   Gravier, T ^a   Kirtsch, J ^a   Monroy, A ^a   Chantre, A ^a  

^a ORANGE LABS   (France)

^b UNIVERSITY OF PADOVA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC; CMOS INTEGRATED CIRCUITS; COST EFFECTIVENESS; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT MANUFACTURE; MASKS; OPTIMIZATION; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; MICROELECTRONICS; PROCESS CONTROL; SEMICONDUCTING SILICON; STATISTICAL METHODS; SURFACE STRUCTURE;

BASE SURFACE ARSENIC COMPENSATION; BIPOLAR JUNCTION TRANSISTOR;

BIPOLAR TRANSISTORS;

EID: 0030274024     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/0026-2714(96)00207-7     Document Type: Article

References (4)

1. S.P. Joshi, R. Lahri, C. Lage, Poly emitter bipolar hot carrier effects in an advanced BiCMOS technology, IEDM Tech. Dig., 182-185, (1987).
2. J. D. Burnett, C. Lage, J.D. Hayden, Bipolar reliability optimization through surface compensation of the base profile, Proc. IEEE/IRPS, 107-111, (1990).
3. A. Granier, M. Laurens, A. Monroy, High performance of a quasi-self-aligned 0.5μm BiCMOS technology, Presented at IEEE MTT&ED, Nov. 1995, France.
4. L. Vendrame, E. Zabotto, A. Dal Fabbro, A. Zanini, G. Verzellesi, E. Zanoni, A. Chantre, P. Pavan, Influence of impact-ionization-induced base current reversal on bipolar transistor parameters, IEEE Trans. Electr. Dev., vol.42, n.9, pp. 1636-1646, (1995).