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Volumn 36, Issue 11-12 SPEC. ISS., 1996, Pages 1747-1750

Copper interconnection lines: Sarf characterization and lifetime test

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; CORRELATION METHODS; DEPOSITION; ELECTRIC RESISTANCE; ELECTROMIGRATION; GRAIN SIZE AND SHAPE; METALLIZING; MICROSTRUCTURE; SILICON; SPECTRUM ANALYSIS; THIN FILMS; TRANSMISSION ELECTRON MICROSCOPY; METALLOGRAPHIC MICROSTRUCTURE; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE TESTING;

EID: 0030274002     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/0026-2714(96)00189-8     Document Type: Article
Times cited : (2)

References (14)
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    • Advanced multilayer metallization schemes with copper as interconnect metal
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  • 4
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    • Budapest
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    • Copper metallizations for integrated circuits: Technology, TEM analysis and electrical characterization
    • submitted for pubblication
    • P. Bruschi, C. Ciofi, V. Dattilo, A. Diligenti, A. Nannini, B. Neri, Copper metallizations for integrated circuits: technology, TEM analysis and electrical characterization, submitted for pubblication on IEEE Trans. Electron Devices.
    • IEEE Trans. Electron Devices
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  • 7
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    • Electrical resistivity model for polycrystalline films: The case of arbitrary reflection at external surfaces
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  • 10
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    • Grain size dependence of electromigration-induced failures in narrow interconnects
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  • 12
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    • Evaluating the large electromigration resistance of copper interconnects employing a newly developed accelerated life-test method
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  • 13
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  • 14
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    • Activation energy for electromigration in Cu films
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.