System-level design for test of fully differential analog circuits

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 10, 1996, Pages 1526-1534

  Stessman, Nicholas J ^b,c,d,e   Vinnakota, Bapiraju ^b,d,f,g,h   Harjani, Ramesh ^{a,b,d,i,j,k,l,m}  

^a IEEE

^b University of Minnesota   (United States)

^c UNIVERSITY OF IOWA   (United States)

^d UNIVERSITY OF MINNESOTA   (United States)

^e ELI LILLY AND COMPANY   (United States)

^f INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

^g PRINCETON UNIVERSITY   (United States)

^h LUCENT TECHNOLOGIES   (United States)

ⁱ BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE   (India)

^j INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

^k CARNEGIE MELLON UNIVERSITY   (United States)

^l MENTOR GRAPHICS CORPORATION   (United States)

^m NONE

more..

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC FILTERS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LINEAR INTEGRATED CIRCUITS;

CHECKER CIRCUITS; CONCURRENT ERROR DETECTION; FULLY DIFFERENTIAL ANALOG CIRCUITS; FULLY DIFFERENTIAL ANALOG CODE;

INTEGRATED CIRCUIT TESTING;

EID: 0030270727     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.540065     Document Type: Article

References (11)

1. B. Vinnakota and R. Harjani, "The design of analog self-checking circuits," presented at IEEE Int. Conf. VLSI Design, 1994.
2. R. Harjani and B. Vinnakota, "Analog circuit observer blocks," presented at 12th IEEE VLSI Test Symp., 1994.
3. V. Kolarik, M. Lubaszewski, and B. Courtois, "Designing self-excersising analogue checkers," in IEEE VLSI Test Symp., 1994.
4. B. Vinnakota, R. Harjani, and N. Stessman, "System-level design for test of fully differential analog circuits," presented at IEEE/ACM Design Automation Conf., 1995.
5. C.-L. Wey, S. Krishnan, and S. Sahli, "Design of concurrent error detectable current-mode A/D converters for real-time applications," Analog Integrated Circuits and Signal Processing, vol. 4, pp. 65-74, 1993, Kluwer Academic Publishers.
6. J. L. Huertas, A. Rueda, and D. Vazquez, "Improving the testability of switched capacitor filters," Analog Integrated Circuits and Signal Processing, vol. 4, pp. 199-213, 1993. Kluwer Academic Publishers.
7. L. T. Wurtz, "Built-in self-test structure for mixed-mode circuits," IEEE Trans. Instrum. Meas., vol. 42, pp. 25-29, Feb. 1993.
8. K. Arabi, B. Kaminska, and J. Rzeszut, "A new built-in self-test approach for digital-to-analog and analog-to-digital converters," presented at IEEE Int. Conf. Computer-Aided Design and Test, 1994.
9. V. Kolarik, M. Lubaszewski, and B. Courtois, "Toward self-checking mixed-signal integrated circuits," presented at European Solid-State Circuits Conf., 1993.
10. B. Vinnakota and R. Harjani, "Analog circuit observer blocks," to appear in IEEE Trans. Circuits Syst., 1996.
11. K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. C. Messerschmidt, "A low-noise chopper-stabilized switched-capacitor filtering technique," IEEE J. Solid-State Circuits, vol. SC-16, pp. 708-715, Dec. 1981.