Dynamic clamp for pull-in time reduction

IEEE Transactions on Instrumentation and Measurement

Volumn 45, Issue 5, 1996, Pages 907-909

  Calleja, Hugo ^a  

^a CENTRO NACIONAL DE INVESTIGACIÓN Y DESARROLLO TECNOLÓGICO   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR CIRCUITS; DIGITAL CIRCUITS; ERRORS; FREQUENCY DIVIDING CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; LAPLACE TRANSFORMS; NUMERICAL METHODS; PHASE LOCKED LOOPS; SIGNAL PROCESSING;

DIGITAL PHASE LOCKED LOOP CIRCUITS; DYNAMIC CLAMP; ERROR REDUCTION; INPUT SIGNAL FREQUENCY; INTERMITTENT SIGNALS; PULL IN TIME REDUCTION;

CLAMPING DEVICES;

EID: 0030270697     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/19.536709     Document Type: Article

References (4)

1. A. Ferraro and R. Ottobino, " A low-cost frequency multiplier for synchronous sampling of periodic signals," IEEE Trans. Instrum. Meas., vol. 41, pp. 203-207, Apr. 1992.
2. High Speed Logic Family Data Handbook, Philips Semiconductors, 1994.
3. R. Volgers, " Phase-locked loop circuits: 74HC/HCT4046A & 74HC/HCT7046A - HCMOS designer's guide," Philips Components.
4. D. Wolaver, Phase-Locked Loop Circuit Design, Englewood Cliffs, NJ: Prentice-Hall, 1991.