A parallel processing chip with embedded DRAM macros

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 10, 1996, Pages 1556-1559

  Sunaga, Toshio ^a   Miyatake, Hisatada ^a   Kitamura, Koji ^a   Kogge, Peter M ^b   Retter, Eric ^c  

^a IBM JAPAN LTD   (Japan)

^b UNIVERSITY OF NOTRE DAME   (United States)

^c LOCKHEED MARTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; LOGIC CIRCUITS; PARALLEL PROCESSING SYSTEMS; RANDOM ACCESS STORAGE;

PARALLEL PROCESSING CHIP; PERIPHERAL CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 0030269463     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.540068     Document Type: Article

References (5)

1. P. M. Kogge, "EXECUBE - A new architecture for scalable MPP's," in Proc. Int. Conf. on Parallel Processing, St. Charles, IL, Aug. 1994, pp. 77-84.
2. P. M. Kogge et al., "Combined DRAM and logic chip for massively parallel systems," presented at 16th Conf. Advanced Research in VLSI, Raleigh, NC, Mar. 1995.
3. N. C. C. Lu et al., "A substrate-plate-trench-capacitor (SPT) memory cell for dynamic RAM's," IEEE J. Solid-State Circuits vol. SC-21, no. 5, pp. 627-634, Oct. 1986.
4. M. D. Weir et al., "A 250K-circuit ASIC family using a DRAM technology," in IEEE CICC Proc., pp. 4.6.1-4.6.5, May 1990.
5. T. Sunaga et al., "DRAM macros for ASIC chips,"IEEE J. Solid-Slate Circuits, vol. 30, no. 9, pp. 1006-1014, Sept. 1995.