Design and analysis of hardware for high-performance prolog

Journal of Logic Programming

Volumn 29, Issue 1-3, 1996, Pages 107-139

  Holmer, Bruce K ^a   Sano, Barton ^a   Carlton, Michael ^a   Van Roy, Peter ^a   Despain, Alvin M ^a  

^a Siemens Components Inc ^*

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; COST EFFECTIVENESS; MICROCOMPUTERS; MICROPROCESSOR CHIPS; PERFORMANCE; PROGRAM COMPILERS; PROLOG (PROGRAMMING LANGUAGE); SYSTEMS ANALYSIS; VLSI CIRCUITS;

PROLOG MACHINES;

COMPUTER HARDWARE;

EID: 0030265096     PISSN: 07431066     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0743-1066(96)88981-3     Document Type: Article

References (37)

1. Beer, J., The Occur-Check Problem Revisited, J. Logic Programming 5(3):243-261 (Sept. 1988).
2. Benker, H., Beacco, J. M., Bescos, S., Dorochevsky, M., Jeffre, Th., Pohimann, A., Noyé, J., Poterie, B., Sexton, A., Syre, J. C., Thibault, O., and Watzalwik, G., KCM: A Knowledge Crunching Machine, in: Proc. 16th Annual Int. Symp. on Computer Architecture, May 1989, pp. 186-194.
3. Bitar, P. and Despain, A. M., Multiprocessor Cache Synchronization, Issues, Innovations, Evolution, in: Proc. 13th Annual Int. Symp. on Computer Architecture, June 1986, pp. 424-433.
4. Borriello, G., Cherenson, A. R., Danzig, P. B., and Nelson, M. N., RISCs vs. CISCs for Prolog: A Case Study, in: Proc. 2nd Symp. on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Oct. 1987, pp. 136-145.
5. Carlson, R., The Bottom-Up Design of a Prolog Architecture, Technical Report UCB/CSD 89/536, University of California, Berkeley, May 1989.
6. Carlton, M., Pendleton, J., Holmer, B. K., Sano, B., and Despain, A. M., Cache and Multiprocessor Support in the BAM Microprocessor, in: Proc. 4th Annual Symp. on Parallel Processing, Apr. 1990.
7. Chang, A. and Mergen, M. F., 801 Storage: Architecture and Programming, ACM Trans. Computer Systems 6(1):28-50 (Feb. 1988).
8. Debray, S. K. and Warren, D. S., Automatic Mode Inference for Prolog Programs, in: Proc. 1986 Symp. on Logic Programming, Sept. 1986, pp. 78-88.
9. Dobry, T. P., A High Performance Architecture for Prolog, Kluwer Academic, 1990.
10. Dorochevsky, M., Noyé, J., and Thibault, O., Has Dedicated Hardware for Prolog a Future?, in: Proc. Processing Declarative Knowledge (PDK'91), 1991, pp. 17-31.
11. Harsat, A. and Ginosar, R., CARMEL-2: A Second Generation VLSI Architecture for Flat Concurrent Prolog, in: Proc. Int. Conf. on Fifth Generation Computer Systems, Dec. 1988, pp. 962-969.
12. Haygood, R., A Prolog Benchmark Suite for Aquarius, Technical Report UCB/CSD 89/509, Computer Science Division, University of California, Berkeley, Apr. 1989.
13. Hennessy, J., Jouppi, N., Przybylski, S., Rowen, C., and Gross, T., Design of a High Performance VLSI Processor, in: Proc. 3rd Caltech Conf. on VLSI, 1983, pp. 33-54.
14. Holmer, B. K. and Despain, A. M., Viewing Instruction Set Design as an Optimization Problem, in: Proc. 24th Annual Workshop on Microprogramming and Microarchitecture (MICRO-24), 1991, pp. 153-162.
15. Holmer, B. K., Sano, B., Carlton, M., Van Roy, P., Haygood, R., Bush, W. R., Despain, A. M., Pendleton, J. M., and Dobry, T., Fast Prolog with an Extended General Purpose Architecture, in: Proc. 17th Annual Int. Symp. on Computer Architecture, 1990, pp. 282-291.
16. Katevenis, M. G. H., Reduced Instruction Set Computer Architectures for VLSI, MIT Press, 1985.
17. Korsloot, M. and Mulder, H., Sequential Architecture Models for Prolog: A Performance Comparison, New Generation Computing 9:201-209 (1991).
18. Mills, J. W., LIBRA: A High-Performance Balanced Computer Architecture for Prolog, Ph.D. thesis, Arizona State University, Dec. 1988.
19. Mills, J. W., A High-Performance LOW RISC Machine for Logic Programming, J. Logic Programming 6(1&2):179-212 (Jan./Mar. 1989).
20. Nakashima, H. and Nakajima, K., Hardware Architecture of the Sequential Inference Machine: PSI-II, in: Proc. 1987 Symp. on Logic Programming, Aug. 1987, pp. 104-113.
21. Pendleton, J., Kong, S., Brown, E., Dunlap, F., Marino, C., Ungar, D., Patterson, D., and Hodges, D., A 32-bit Microprocessor for Smalltalk, IEEE J. Solid State Circuits SC-21(5):741-749 (Oct. 1986).
22. Radin, G., The 801 Minicomputer, in: Proc. Symp. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Mar. 1982, pp. 39-47.
23. Sano, B., Performance vs. Cost of the BAM, Technical Report TR-89-01, Advanced Computer Architecture Laboratory, University of Southern California, Dec. 1989.
24. Seo, K. and Yokota, T., Design and Fabrication of Pegasus Prolog Processor, in: Proc. VLSI 89, 1989.
25. Srini, V. P., Tam, J. V., Nguyen, T. M., Patt, Y. N., Despain, A. M., Moll, M., and Ellsworth, D., A CMOS Chip for Prolog, in: Proc. Int. Conf. on Computer Design, Oct. 1987, pp. 605-610.
26. Steenkiste, P. and Hennessy, J., Tags and Type Checking in LISP: Hardware and Software Approaches, in: Proc. 2nd Symp. on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Oct. 1987, pp. 50-59.
27. Sterling, L. and Shapiro, E., The Art of Prolog, MIT Press, 1986.
28. Taylor, A., High Performance Prolog Implementation, Ph.D. thesis, University of Sydney, June 1991.
29. Touati, H. and Despain, A., An Empirical Study of the Warren Abstract Machine, in: Proc. 1987 Symp. on Logic Programming, Aug. 1987, pp. 114-124.
30. Ungar, D. M., The Design and Evaluation of a High Performance Smalltalk System, MIT Press, 1987.
31. Van Roy, P., An Intermediate Language to Support Prolog's Unification, in: E. Lusk and R. A. Overbeek (eds.), Proc. North American Conf. on Logic Programming, MIT Press, Oct. 1989, pp. 1148-1164.
32. Van Roy, P., 1983-1993: The Wonder Years of Sequential Prolog Implementation, J. Logic Programming 19/20:385-441 (May/July 1994).
33. Van Roy, P., Demoen, B., and Willems, Y. D., Improving the Execution Speed of Compiled Prolog with Modes, Clause Selection, and Determinism, in: TAPSOFT'87, Lecture Notes in Computer Sciences, 250, Mar. 1987, pp. 111-125.
34. Van Roy, P. and Despain, A. M., High-Performance Logic Programming with the Aquarius Prolog Compiler, Computer 25(1):54-68 (Jan. 1992).
35. Van Roy, P., Can Logic Programming Execute as Fast as Imperative Programming?, Ph.D. thesis, University of California, Berkeley, Dec. 1990. Available as U. C. Berkeley Computer Science Division Technical Report UCB/CSD 90/600.
36. Warren, D. H. D., An Abstract Prolog Instruction Set, Technical Report 309, SRI International, Oct. 1983.
37. Yokota, M., Yamamoto, A., Taki, K., Nishikawa, H., and Uchida, S., The Design and Implementation of a Personal Sequential Inference Machine: PSI, New Generation Computing 125-144 (1983).