Superconducting complementary output switching logic operating at 5-10 Gb/s

Applied Physics Letters

Volumn 69, Issue 18, 1996, Pages 2746-2748

  Jeffery, Mark ^a   Perold, Willem ^a,b   Van Duzer, T ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b STELLENBOSCH UNIVERSITY   (South Africa)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; COMPUTER SIMULATION; JOSEPHSON JUNCTION DEVICES; LOGIC CIRCUITS; MONTE CARLO METHODS; NATURAL FREQUENCIES; OPTIMIZATION; SQUIDS; SWITCHING; TIMING CIRCUITS;

COMPLEMENTARY OUTPUT SWITCHING LOGIC; INDUCTANCE; JOSEPHSON JUNCTION; TWO BIT ENCODER CIRCUIT;

LOGIC GATES;

EID: 0030264338     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.117698     Document Type: Article

References (12)

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