Inverter delay modelling for submicrometre CMOS process

Electronics Letters

Volumn 32, Issue 22, 1996, Pages 2070-2071

  Daga, J M ^a   Turgis, S ^a   Auvergne, D ^a  

^a LIRMM   (France)

Author keywords

CMOS integrated circuits; Delays; Invertors; Simulation

Indexed keywords

CAPACITANCE; CHARGE CARRIERS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COUPLED CIRCUITS; DELAY CIRCUITS; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MATHEMATICAL MODELS; MICROMETERS; SHORT CIRCUIT CURRENTS;

COUPLING RESISTANCE; SOFTWARE PACKAGE HSPICE;

ELECTRIC INVERTERS;

EID: 0030260010     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19961394     Document Type: Article

References (3)

1. JEPPSON, K.O.: 'Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay', IEEE J. Solid State Circuits, 1994, 29, (6), pp. 646-654
2. SAKURAI, T., and NEWTON, A.R.: 'Alpha-power model, and its application to CMOS inverter delay and other formulas', IEEE J. Solid State Circuits, 1990, 25, pp. 584-594
3. AUVERGNE, D., DESCHACHT, D., and ROBERT, M.: 'Explicit formulation of delays in CMOS VLSI', Electron. Lett., 1987, 23, (14), pp. 741-742