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Volumn 32, Issue 19, 1996, Pages 1748-1749

Transitional gate delay detection for combinational circuits using a genetic algorithm

Author keywords

Combinational circuits; Genetic algorithms

Indexed keywords

COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; ERROR DETECTION; FAILURE ANALYSIS; GENETIC ALGORITHMS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; MATHEMATICAL MODELS;

EID: 0030247450     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19961184     Document Type: Article
Times cited : (2)

References (9)
  • 2
    • 0026896741 scopus 로고
    • An efficient delay test generation system for combinational logic circuits
    • PARK, E.S., and MERCER, M.R.: 'An efficient delay test generation system for combinational logic circuits'. IEEE Trans. Computer-Aided Des. Int. Circuits Syst., 1992, 11, (7), pp. 926-938
    • (1992) IEEE Trans. Computer-Aided Des. Int. Circuits Syst. , vol.11 , Issue.7 , pp. 926-938
    • Park, E.S.1    Mercer, M.R.2
  • 4
    • 0028425613 scopus 로고
    • Generating test patterns for VLSI circuits using a genetic algorithm
    • O'DARE, M.J., and ARSLAN, T.: 'Generating test patterns for VLSI circuits using a genetic algorithm'. Electron. Lett., 1994, 30, (10), pp. 778-779
    • (1994) Electron. Lett. , vol.30 , Issue.10 , pp. 778-779
    • O'Dare, M.J.1    Arslan, T.2
  • 7
    • 0028712078 scopus 로고
    • A genetic approach to test generation for logic circuits
    • Nara, Japan, November
    • HAYASHI, T., HIDEHIKO, K., and HATAYAMA, K.: 'A genetic approach to test generation for logic circuits'. Proc. 3rd Asian Test Symp., Nara, Japan, November 1994, pp. 101-106
    • (1994) Proc. 3rd Asian Test Symp. , pp. 101-106
    • Hayashi, T.1    Hidehiko, K.2    Hatayama, K.3
  • 8
    • 0029190018 scopus 로고
    • Hierarchical test pattern generation using a genetic algorithm with a dynamic global reference table
    • 12-14 September
    • O'DARE, M.J., and ARSLAN, T.: 'Hierarchical test pattern generation using a genetic algorithm with a dynamic global reference table'. First IEE/IEEE Int. Conf. Genetic Algorithms in Eng. Syst.: Innovations Appl., 12-14 September 1995, Vol. 414, pp. 517-523
    • (1995) First IEE/IEEE Int. Conf. Genetic Algorithms in Eng. Syst.: Innovations Appl. , vol.414 , pp. 517-523
    • O'Dare, M.J.1    Arslan, T.2
  • 9
    • 0028397228 scopus 로고
    • A new dynamic test vector compaction for automatic test pattern generation
    • AYARI, B., and KAMINSKA, B.: 'A new dynamic test vector compaction for automatic test pattern generation'. IEEE Trans. Comput.-Aided Design, 1994, 13, pp. 353-358
    • (1994) IEEE Trans. Comput.-Aided Design , vol.13 , pp. 353-358
    • Ayari, B.1    Kaminska, B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.