A new digital pll for the class i partial response channel

IEEE Transactions on Magnetics

Volumn 32, Issue 5 PART 1, 1996, Pages 3974-3976

  Fukuda, Shinichi ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BLOCK CODES; DECODING; DIGITAL CIRCUITS; DIGITAL STORAGE; INTERPOLATION; LSI CIRCUITS; NYQUIST DIAGRAMS; OSCILLATORS (ELECTRONIC); SAMPLING; SIGNAL TO NOISE RATIO; TIMING CIRCUITS;

CHANNEL CLOCK GENERATOR; DIGITAL PHASE LOCKED LOOPS; NYQUIST CHARACTERISTICS; RING OSCILLATOR;

PHASE LOCKED LOOPS;

EID: 0030246798     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/20.539235     Document Type: Article

References (5)

1. S. Fukuda, H. Hirasaka, Y. Okazaki and J. Honda, "High Density Digital Magnetic Recording Using Class I Partial Response and 8-10 Block Code", 1ERE Trans. MAG, vol. 31, No. 6, pp 3039 3041, November 1995.
2. International Standard, "IS 12247", ISO/IEC, 1993.
3. International Standard, "IS 13923", ISO/IEC, 1995.
4. H. Hirasaka, A. Tanaka, K. Nomura and S. Fukuda, "An Adaptive Equalizer for the Class I Partial Response Channel Used by DDS3", 1996 Digests of INTEKMAG '96, HB-5, April 1996.
5. S. Fukuda, T. Fukami and A. Moroboshi, "New Digital PLL for 8/10 Modulation Code Used by DAT', AES the 93rd convention, October 1992.