Unified mixed radix 2-4 redundant CORDIC processor

IEEE Transactions on Computers

Volumn 45, Issue 9, 1996, Pages 1068-1073

  Antelo, Elisardo ^b   Bruguera, Javier D ^a,b   Zapata, Emilio L ^a,c  

^a IEEE

^b UNIVERSITY OF SANTIAGO DE COMPOSTELA   (Spain)

^c UNIVERSITY OF MÁLAGA   (Spain)

Author keywords

Elementary functions; High speed processor; Pipelined design; Redundant arithmetic; Unified CORDIC algorithm

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; ESTIMATION; ITERATIVE METHODS; PIPELINE PROCESSING SYSTEMS; VECTORS;

CARRY SAVE ARITHMETIC; ELEMENTARY FUNCTIONS; HIGH SPEED PROCESSOR; MICROROTATION; REDUNDANT ARITHMETIC; UNIFIED CORDIC ALGORITHM;

PROGRAM PROCESSORS;

EID: 0030245110     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.537131     Document Type: Article

References (17)

1. H.M. Ahmed, J.M. Delsome, and M. Morf, "Highly Concurrent Computing Structures for Matrix Arithmetic and Signal Processing, Computer, pp. 65-82, Jan. 1982.
2. J.D. Bruguera, E. Antelo, and E.L. Zapata, "Design of a Pipelined Radix 4 CORDIC Processor," J. Parallel Computing, vol. 19, no. 7, pp. 729-744, 1993.
3. J.R. Cavallaro and F.T. Luk, "CORDIC Arithmetic for an SVD Processor," J. Parallel and Distributed Computing, no. 5, pp. 271-290, 1988.
4. H. Dawid and H. Meyr, "High Speed Bit-Level Pipelined Architectures for Redundant CORDIC Implementation," Proc. ASAP 92, pp. 358-372, 1992.
5. A.M. Despain, "Fourier Transform Computers Using CORDIC Iterations," IEEE Trans. Computers, vol. 23, pp. 993-1,001, Oct. 1974.
6. J. Duprat and J.-M. Muller, "The CORDIC Algorithm: New Results for Fast VLSI Implementation," IEEE Trans. Computers, vol. 42, no. 2, pp. 168-178, Feb. 1993.
7. M.D. Ercegovac and T. Lang, "Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD," IEEE Trans. Computers, vol. 39, no. 6, pp. 725-740, June 1990.
8. M.D. Ercegovac and T. Lang, "Simple Radix 4 Division with Operands Scaling," IEEE Trans. Computers, vol. 39, no. 9, pp. 1,204-1,208, Sept. 1990.
9. M. Ercegovac and T. Lang, Division and Square Root: Digit-Recurrence, Algorithms and Implementations. Kluwer Academic, 1994.
10. Y.H. Hu, "CORDIC-Based VLSI Architecture for Digital Signal Processing," IEEE Signal Processing Magazine, no. 7, pp. 16-35, July 1992.
11. K. Kota and J.R. Cavallaro, "Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special Purpose Processors," IEEE Trans. Computers, vol. 42, no. 7, pp. 769-779, July 1993.
12. J.-A. Lee and T. Lang, "Constant-Factor Redundant CORDIC for Angle Calculation and Rotation," IEEE Trans. Computers, vol. 41, no. 8, pp. 1,016-1,025, Aug. 1992.
13. T.G. Noll, "Carry-Save Architectures for High Speed Signal Processing," J. VLSI Signal Processing, vol. 3, pp. 121-140, 1991.
14. N. Takagi, T. Asada, and S. Yajima, "Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation," IEEE Trans. Computers, vol. 40, no. 9, pp. 989-995, Sept. 1991.
15. D. Timmermann, H. Hahn, and B.J. Hosticka, "Low Latency Time CORDIC Algorithms," IEEE Trans. Computers, vol. 41, no. 8, pp. 1,010-1,015, Aug. 1992.
16. J.E. Volder, "The CORDIC Trigonometric Computing Technique," IRE Trans. Electronic Computers, vol. 8, pp. 330-334, Sept. 1959.
17. J.S. Walther, "A Unified Algorithm for Elementary Functions," Proc. Spring. Joint Computing Conf., pp. 379-385, 1971.