Computer-aided design of fault-tolerant VLSI systems

IEEE Design and Test of Computers

Volumn 13, Issue 3, 1996, Pages 88-96

  Karri, Ramesh ^a,b,c   Hogstedt, Karin ^b,d,e   Orailoglu, Alex ^b,d,f  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c University of Massachusetts   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e LUND INSTITUTE OF TECHNOLOGY   (Sweden)

^f UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; ELECTRIC NETWORK SYNTHESIS; HIGH LEVEL LANGUAGES; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

CONTROL DATAFLOW GRAPH; FAULT TOLERANT VLSI CIRCUITS; SELF RECOVERY CAPABILITY;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 0030242652     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.536099     Document Type: Article

References (14)

1. Y. Tamir and M. Tremblay, "High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback," IEEE Trans. Computers, Vol. 39, No. 4, 1990, pp. 548-554.
2. M.M. Yen, W.K. Fuchs, and J.A. Abraham, "Designing for Concurrent Error Detection in VLSI: Application to a Microprogram Control Unit," IEEE J. Solid State Circuits, Vol. 22, No. 4, 1987, pp. 595-605.
3. C. Hu, "The Berkeley Reliability Simulator BERT: An IC Reliability Simulator," Microelectronics J., Vol. 23, No. 2, 1992, pp. 97-102.
4. M.M. Tsao and D.P. Siewiorek, "The Design of C.fast: A Single Chip Fault-Tolerant Microprocessor," Proc. 12th Int'l Symp. Fault-Tolerant Computing, IEEE Computer Society Press, Los Alamitos, Calif., 1982, pp. 63-69.
5. R. Karri and A. Orailoglu, "Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs," Proc. 22nd Int'l Symp. Fault-Tolerant Computing IEEE CS Press, 1992, pp. 519-526.
6. A. Orailoglu and R. Karri, "A Design Methodology for the High-Level Synthesis of Fault-Tolerant ASICs," VLSI Signal Processing, Vol. 5, Oct. 1992, pp. 417-426.
7. A. Orailoglu and D.D. Gajski, "Flow Graph Representation," Proc. 23rd Design Automation Conf., IEEE CS Press, 1986, pp. 503-506.
8. J.S. Lis and D.D. Gajski, "Synthesis from VHDL," Proc. Int'l Conf. Computer Design, IEEE CS Press, 1988, pp. 378-381.
9. A. Casotto, OCTTOOLS 5.1: The User Guide, Electronics Research Laboratory, UC Berkeley, Berkeley, Calif., 1991.
10. A. Orailoglu and R. Karri, "Coactive Scheduling and Checkpoint Determination During High-Level Synthesis of Self-Recovering Microarchitectures," IEEE Trans. VLSI Systems, Vol. 2, No. 3, 1994, pp. 304-311.
11. A. Orailoglu and R. Karri, "Automatic Synthesis of Self-Recovering VLSI Systems," IEEE Trans. Computers, Vol. 45, No. 2, Feb. 1996, pp. 110-118.
12. D.P. Siewiorek and R.S. Swarz, The Theory and Practice of Reliable System Design, Digital Press, Bedford, Mass., 1989.
13. J. Klion, Practical Electronic Reliability Engineering, Van Nostrand Reinhold, New York, 1992.
14. L.M. Guerra, M.M. Potkonjak, and J.M. Rabaey, "High-Level Synthesis for Reconfigurable Datapath Structures," Proc. 1993 IEEE Int'l Conf. Computer-Aided Design, IEEE CS Press, 1993, pp. 26-29.