Configurable digit-serial convolver of type F

Microelectronics Journal

Volumn 27, Issue 6, 1996, Pages 559-566

  Milentijević, Ivan Z ^a   Stojčev, Mile K ^a   Maksimović, Dejan M ^a  

^a UNIVERSITY OF NI   (Serbia)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; DIGITAL ARITHMETIC; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK TOPOLOGY; FAULT TOLERANT COMPUTER SYSTEMS; PARALLEL PROCESSING SYSTEMS;

BIT PARALLEL VERSION; DIGIT SERIAL CONVOLVER; DIOGENES METHOD; INPUT DATA FEEDING; PROCESSING ELEMENTS; SEMI SYSTOLIC ARCHITECTURE;

SYSTOLIC ARRAYS;

EID: 0030242372     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/0026-2692(95)00115-8     Document Type: Article

References (8)

1. H.T. Kung, Why systolic architectures, IEEE Computer, 15 (1982) 37-46.
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3. T. Noll, Semi-systolic maximum rate transversal filters with programmable coefficients, Workshop of Systolic Architectures, Oxford, 1986, pp. 103-112.
4. D. Reurer and H. Klar, A configurable convolution chip with programmable coefficients, IEEE J. Solid-State Circuits, 27(7) (1992) 1121-1123.
5. R. Hartley and P. Corbett, A digit-serial processing technique, IEEE Trans. Circuits Syst., 37(6) (1990) 709-719.
6. R. Negrini and M.G. Sami, Fault-tolerance Through Reconfiguration of VLSI and WSI Arrays, MIT Press, Cambridge, 1989.
7. A.L. Rosenberg, The Diogenes approach to testable fault-tolerant arrays of processors, IEEE Trans. Computers, C-32(10) (1983) 902-910.
8. I.Z. Milentijević, Fault tolerant digit-serial semi-systolic array intended for convolution, M. Sc. Thesis, Faculty of Electronic Engineering, University of Niš, Serbia, 1994.