A CCD/CMOS focal-plane array edge detection processor implementing the multiscale veto algorithm

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 9, 1996, Pages 1239-1247

  McIlrath, Lisa Dron ^{a,b,c,d,e,f,g,h}  

^a IEEE

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^c Northeastern University   (United States)

^d MIT MEDIA LAB   (United States)

^e UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^f LUCENT TECHNOLOGIES   (United States)

^g NORTHEASTERN UNIVERSITY   (United States)

^h UNIVERSITY OF TEXAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CHARGE COUPLED DEVICES; CMOS INTEGRATED CIRCUITS; COMPUTER VISION; EDGE DETECTION; IMAGE PROCESSING; PROGRAM PROCESSORS;

ANALOG CIRCUITS; CHARGE LOADING; CHARGE REMOVAL; FOCAL PLANE PROCESSOR; IMAGE ACQUISITION; IMAGE SMOOTHING; MULTISCALE VETO EDGE DETECTION ALGORITHM;

PARALLEL PROCESSING SYSTEMS;

EID: 0030241005     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.535407     Document Type: Article

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