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Volumn 20, Issue 5, 1996, Pages 277-284

Minimal pipeline architecture - An alternative to superscalar architecture

Author keywords

Computer architecture; Pipelining; Superscalar processor; VLIW

Indexed keywords

INTERCONNECTION NETWORKS; MICROCOMPUTERS; PIPELINE PROCESSING SYSTEMS;

EID: 0030231362     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/0141-9331(96)01092-7     Document Type: Article
Times cited : (10)

References (13)
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    • Measuring the parallelism available for very long instruction word architectures
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    • Nicolau, A.1    Fisher, J.2
  • 9
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    • IMPACT: An architectural framework for multiple-instruction-issue processors
    • May 27-30, Toronto, Association for Computing Machinery, New York
    • P. Chang, S. Mahlke, W. Chen, N. Warter and W. Hwu, IMPACT: An architectural framework for multiple-instruction-issue processors, in Proc. 18th Annual Int. Symp. on Computer Architecture, May 27-30, 1991, Toronto, Association for Computing Machinery, New York, pp. 266-275.
    • (1991) Proc. 18th Annual Int. Symp. on Computer Architecture , pp. 266-275
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    • SuperDLX - A generic superscalar simulator
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.