Precise delay generation using the Vernier technique

Electronics Letters

Volumn 32, Issue 18, 1996, Pages 1658-1659

  Moyer, G C ^a   Clements, M ^a   Liu, W ^a  

^a North Carolina State University   (United States)

Author keywords

CMOS integrated circuits; Delay circuits

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT TESTING; OSCILLATORS (ELECTRONIC);

CONVENTIONAL DELAY GENERATION METHODS; COUPLED RING OSCILLATORS; SYNCHRONIZING CIRCUITS; VERNIER TECHNIQUE;

DELAY CIRCUITS;

EID: 0030218345     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19961149     Document Type: Article

References (3)

1. KIM, B., HELMAN, D., and GRAY, P.R.: 'A 30-MHz hybrid analog/ digital clock recovery circuit in 2-/mμm CMOS', IEEE J. Solid-State Circuits, 1990, 25, (6), pp. 1385-1394
2. YAMANAKA, N., and KIKUCHI, S.: 'Gbit/s programmable delay-line IC for high-speed pipelining data transmission', Trans. IEICE, 1989, 72, (6), pp. 695-697
3. MANEATIS, J., and HOROWITZ, M.A.: 'Precise delay generation using coupled oscillators', IEEE J. Solid-State Circuits, 1993, 28, (12), pp. 1273-1282