Optimizing high voltage bipolar transistors in a smart-power complementary BiCMOS technology

Solid-State Electronics

Volumn 39, Issue 8, 1996, Pages 1185-1191

  Ryter, R ^a   Zingg, R ^a   Fichtner, W ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

COLLECTOR BASE DEPLETION REGION; HIGH VOLTAGE BIPOLAR TRANSISTORS; IMPACT IONIZATION; TRANSISTOR GAIN;

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC VARIABLES MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; OPTIMIZATION; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING;

BIPOLAR TRANSISTORS;

EID: 0030216554     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/0038-1101(95)00416-5     Document Type: Review

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