Dynamic data retention and implied design criteria for floating-body SOI DRAM

IEEE Electron Device Letters

Volumn 17, Issue 8, 1996, Pages 385-387

  Suh, Dongwook ^b   Fossum, Jerry G ^a,b   Pelella, Mario M ^a,c  

^a IEEE

^b University of Florida   (United States)

^c IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; ELECTRIC DISCHARGES; GATES (TRANSISTOR); MOSFET DEVICES; PRODUCT DESIGN; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY;

DATA RETENTION; DYNAMIC RANDOM ACCESS MEMORY; FLOATING BODY EFFECTS; NODAL EQUATION; TRANSIENT PARASITIC CURRENT;

RANDOM ACCESS STORAGE;

EID: 0030215218     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.511583     Document Type: Article

References (8)

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