-
2
-
-
0016961574
-
On Monte Carlo Testing of Logic Networks
-
June
-
P. Agrawal and V.D. Agrawal, "On Monte Carlo Testing of Logic Networks," IEEE Trans. Computers, vol. 15, pp. 664-667, June 1976.
-
(1976)
IEEE Trans. Computers
, vol.15
, pp. 664-667
-
-
Agrawal, P.1
Agrawal, V.D.2
-
4
-
-
0025487032
-
Built-In Self-Test with Weighted Random Pattern Hardware
-
F. Brglez, C. Gloster and G. Kedem, "Built-In Self-Test with Weighted Random Pattern Hardware," Proc. ICCD, pp. 161-166, 1990.
-
(1990)
Proc. ICCD
, pp. 161-166
-
-
Brglez, F.1
Gloster, C.2
Kedem, G.3
-
6
-
-
84961240995
-
Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
-
S. Hellebrand, S. Tarnick, J. Rajski and B. Courtois, "Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," Proc. IEEE Int'l Test Conf., pp. 120-129, 1992.
-
(1992)
Proc. IEEE Int'l Test Conf.
, pp. 120-129
-
-
Hellebrand, S.1
Tarnick, S.2
Rajski, J.3
Courtois, B.4
-
8
-
-
0027666397
-
Analysis of Signal Probability in Logic Circuits Using Stochastic Models
-
Sept.
-
A. Majumdar and S.B.K. Vrudhula, "Analysis of Signal Probability in Logic Circuits Using Stochastic Models," IEEE Trans. VLSI Systems, vol. 1, pp. 365-379, Sept. 1993.
-
(1993)
IEEE Trans. VLSI Systems
, vol.1
, pp. 365-379
-
-
Majumdar, A.1
Vrudhula, S.B.K.2
-
10
-
-
0025480231
-
A New Procedure for Weighted Random Built-In Self-Test
-
F. Muradali, V.K. Agarwal, and B. Nadeau-Dostie, "A New Procedure for Weighted Random Built-In Self-Test," Proc. IEEE Int'l Test Conf., pp. 660-669, 1990.
-
(1990)
Proc. IEEE Int'l Test Conf.
, pp. 660-669
-
-
Muradali, F.1
Agarwal, V.K.2
Nadeau-Dostie, B.3
-
12
-
-
0026175735
-
Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-Level Circuits
-
S. Pateras and J. Rajski, "Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-Level Circuits," Proc. 28th ACM/IEEE Design Automation Conf., pp. 347-352, 1991.
-
(1991)
Proc. 28th ACM/IEEE Design Automation Conf.
, pp. 347-352
-
-
Pateras, S.1
Rajski, J.2
-
13
-
-
0026675962
-
Cube-Contained Random Patterns and Their Application to the Complete Testing of Synthesized Multi-Level Circuits
-
S. Pateras and J. Rajski, "Cube-Contained Random Patterns and Their Application to the Complete Testing of Synthesized Multi-Level Circuits," Proc. IEEE Int'l Test Conf., pp. 473-482, 1991.
-
(1991)
Proc. IEEE Int'l Test Conf.
, pp. 473-482
-
-
Pateras, S.1
Rajski, J.2
-
14
-
-
0026128883
-
Test Efficiency Analysis of Random Self-Test of Sequential Circuits
-
Mar.
-
S. Sastry and A. Majumdar, "Test Efficiency Analysis of Random Self-Test of Sequential Circuits," IEEE Trans. Computer Aided Design, vol. 10, pp. 390-398, Mar. 1991.
-
(1991)
IEEE Trans. Computer Aided Design
, vol.10
, pp. 390-398
-
-
Sastry, S.1
Majumdar, A.2
-
16
-
-
0024627841
-
A Method for Generating Weighted Random Patterns
-
Mar.
-
J.A. Waicukauski, E. Lindbloom, E.B. Eichelberger, and O.P. Forlenza, "A Method for Generating Weighted Random Patterns," IBM. J. Res. Develop., pp. 149-161, Mar. 1989.
-
(1989)
IBM. J. Res. Develop.
, pp. 149-161
-
-
Waicukauski, J.A.1
Lindbloom, E.2
Eichelberger, E.B.3
Forlenza, O.P.4
-
18
-
-
0025442153
-
Multiple Distribution for Biased Random Test Patterns
-
June
-
H.J. Wuderlich, "Multiple Distribution for Biased Random Test Patterns," IEEE Trans. Computer-Aided Design, vol. 9, pp. 584-593, June 1990.
-
(1990)
IEEE Trans. Computer-Aided Design
, vol.9
, pp. 584-593
-
-
Wuderlich, H.J.1
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