Parallel pixel processing using programmable gate arrays

Electronics Letters

Volumn 32, Issue 17, 1996, Pages 1557-1559

  Budgett, D M ^a   Tang, P E ^b   Sharp, J H ^a   Chatwin, C R ^c   Young, R C D ^c   Wang, R K ^a   Scott, B F ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c UNIVERSITY OF SUSSEX   (United Kingdom)

Author keywords

Image processing; Parallel algorithms; Programmable logic devices

Indexed keywords

FEATURE EXTRACTION; IMAGE ANALYSIS; LOGIC GATES; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; VIDEO SIGNAL PROCESSING;

HIGH FRAME RATE VIDEO IMAGES; IMAGE PROCESSING ALGORITHMS; PARALLEL PIXEL PROCESSING PATHS; PROGRAMMABLE GATE ARRAYS (PGAS); RECONFIGURABLE HARDWARE DESIGN;

IMAGE PROCESSING;

EID: 0030214443     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19961025     Document Type: Article

References (2)

1. BUDGETT, D.M., SHARP, J.H., TANG, P.C., and CHATWIN, C.R.: 'Implementation of a High Speed Optical/Digital Correlator System'. Optique et Information, European Optical Society Topical Digest Series, 1995, Vol. 6, p. 2.2
2. SHARP, J.H., BUDGETT, D.M., TANG, P.C., and CHATWIN, C.R.: 'Automated recording system for page oriented volume holographic memories', Rev. Sci. Instrum., 1995, 66, pp. 5174-5177