GaAs dynamic memory design

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 8, 1996, Pages 1193-1196

  Law, Oscar M K ^a,b   Salama, C André T ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE CURRENTS; MESFET DEVICES; MOSFET DEVICES; RANDOM ACCESS STORAGE; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTOR DEVICE STRUCTURES;

DYNAMIC MEMORY CELL; SUBTHRESHOLD LEAKAGE LOSS;

SEMICONDUCTOR STORAGE;

EID: 0030214311     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508269     Document Type: Article

References (8)

1. H. Makino, S. Mastsue, M. Noda, N. Tanino, S. Takano, K. Nishitani, and S. Kayano, "A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature," IEEE J. Solid-State Circuits, vol. 25, pp. 1232-1238, 1990.
2. M. Suzuki, S. Notomi, M. Ono, N. Kobayashi, E. Mitani, K. Odani, T. Mimura, and M. Abe, "A 1.2 ns HEMT 64-kb SRAM," IEEE J. Solid-State Circuits, vol. 26, pp. 1571-1575, 1991.
3. J. W. Pabst, T. E. Dungan, J. A. Cooper, Jr., and M. R. Melloch, "Ionimplanted p-n junction capacitors for GaAs DRAM's," IEEE Trans. Electron Devices, vol. 37, pp. 804-806, 1990.
4. T. E. Dungan, P. G. Neudeck, M. R. Melloch, and J. A. Cooper, Jr., "One-transistor GaAs MESFET- and JFET-accessed dynamic RAM cells for high-speed medium density applications," IEEE Trans. Electron Devices, vol. 37, pp. 1599-1607, 1990.
5. R. C. Foss and R. Harland, "Peripheral Circuits for One-Transistor Cell MOS RAM's," IEEE J. Solid-State Circuits, vol. SC-10, pp. 255-261, 1975.
6. E. Arai and N. Ieda, "A 64-kbit dynamic MOS DRAM," IEEE J. Solid-State Circuits, vol. SC-13, pp. 333-338, 1978.
7. O. M. K. Law, "GaAs high speed digital circuits: Dynamic logic and memory design," Ph.D. Thesis, University of Toronto, 1995.
8. C. T. M. Chang, T. Vrotsos, M. T. Frizzell, and R. Carroll, "A Subthreshold Current Model for GaAs MESFET's," IEEE Electron Device Lett., vol. EDL-8, pp. 69-72, 1987.