Delay propagation effect in transistor gates

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 8, 1996, Pages 1184-1189

  Deschacht, Denis ^a   Dabrin, Christophe ^a   Auvergne, Daniel ^a  

^a LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; EQUIVALENT CIRCUITS; OPTIMIZATION; VLSI CIRCUITS;

SIGNAL PROPAGATION; SOFTWARE PACKAGE HSPICE; SWITCHING DELAYS;

GATES (TRANSISTOR);

EID: 0030213826     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508267     Document Type: Article

References (13)

1. K. C. Saraswat and F. Mohammedi, "Effect of scaling of interconnections on the time delay of VLSI circuits," IEEE Trans. Electron Devices, vol. ED-29, pp. 275-280, Apr. 1982.
2. C. Y. Wu and M. C. Shiau, "A new interconnection delay model considering the effects of short-channel logic gates," in Proc. IEEE Int. Symp. Circuits Syst., June 1988, pp. 2847-2850.
3. M. C. Shiau and C. Y. Wu, "The signal delay in interconnection lines considering the effects of small-geometry CMOS inverters," IEEE Trans. Circuits Syst., vol. 37, pp. 420-425, Mar. 1990.
4. C. Y. Wu and M. C. Shiau, "Delay models and speed improvement techniques for RC tree Interconnections among small-geometry CMOS inverters," IEEE J. Solid-State Circuits, vol. 25, no. 5, Oct. 1990.
5. M. Nekili and Y. Savaria, "Optimal methods of driving interconnections in VLSI circuits," in Proc. IEEE Int. Symp. Circuits and Systems, San Diego, May 1992, pp. 21-24.
6. J. L. Wyatt, Jr. and Q. Yu, "Signal delay in RC meshes, trees and lines", in Proc. IEEE Int. Conf. Computer Aided Design, Santa Clara, CA, Nov. 1984, pp. 15-17.
7. J. L. Wyatt, Jr., "Signal delay in RC mesh networks," IEEE Trans. Circuits Syst., vol. CAS-32, pp. 507-510, May 1985.
8. Q. Yu, J. L. Wyatt, Jr., C. Zukowski, H. N. Tan, and P. O'Brien, "Improved bounds on signal delay in linear RC models for MOS interconnect," in Proc. IEEE Int. Symp. Circuits Syst., Kyoto, Japan, June 1985, pp. 903-906.
9. M. Passlack, M. Uhle, and H. Elschner, "Analysis of propagation delays in high-speed VLSI circuits using a distributed line model," IEEE Trans. Computer-Aided Design, vol. 9, no. 8, pp. 821-826, Aug. 1990.
10. D. Deschacht, M. Robert, and D. Auvergne, "Explicit formulation of delays on CMOS data paths," IEEE J. Solid-State Circuits, vol. 23, no. 5, pp. 1257-1264, Oct. 1988.
11. _, "Synchronous mode modeling of delay time in CMOS structures," IEEE J. Solid-State Circuits, vol. 26, pp. 789-795, May 1991.
12. N. Azemard, V. Bonzom, and D. Auvergne, "P. SIZE: A sizing aid for optimized designs" in Proc. European Design Automation Conf., Hamburg, Sept. 1992, pp. 160-165.
13. D. Deschacht, C. Dabrin, and D. Auvergne, "Interconnect delay model with performance optimization emphasis," in Proc. IV Int. Design Automation Workshop, Moscow, Russia, June 1994, pp. 59-61.