Augmented binary hypercube: A new architecture for processor management

IEEE Transactions on Computers

Volumn 45, Issue 8, 1996, Pages 980-984

  Lalgudi, Hari ^b   Akyildiz, Ian F ^a,c   Yalamanchili, Sudhakar ^a,c  

^a IEEE

^b CSI Zeitnet   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Augmented binary hypercube; Ideal mapping; Resource management traffic; Update algorithms

Indexed keywords

COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK TOPOLOGY; FAULT TOLERANT COMPUTER SYSTEMS; MATHEMATICAL MODELS; PARALLEL ALGORITHMS; PROGRAM PROCESSORS; STORAGE ALLOCATION (COMPUTER);

AUGMENTED BINARY HYPERCUBE ARCHITECTURE; IDEAL MAPPING; MANAGEMENT NODES; RESOURCE MANAGEMENT TRAFFIC;

COMPUTER ARCHITECTURE;

EID: 0030212812     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.536241     Document Type: Article

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